College of Engineering & Management, Kolaghat

Contact Information

• Office Phone No.: 03228-250972, Extn - 1509
• Personal Phone No.: 9434418112
• Qtrs No.: C-40/3, KTPP Township

Research Area

• Power Minimization in VLSI Testing

Subjects Taken

• Undergraduate Level: Introduction to Computing, Programming for Problem Solving, Data Structure & Algorithm, Formal Language & Automata Theory, Computer Organization & Architecture, Advanced Architecture, Language Translator, Computer Networks, Inter-networking, Distributed Computing and Personality Development.

Educational Qualification

• Ph. D in E & ECE from IIT, Kharagpur in 2015
• M. E. in Computer Science and Engineering from Jadavpur University in 1998 with 1st class
• B. Tech. in Computer Science and Engineering from Calcutta University in 1996 with 1st class
• B. Sc. in Physics (Hons) from Calcutta University in 1992 with 1st class

Experience

• Teaching: Assistant Professor in CEM Kolaghat, 06/09/2003 - till date
• Teaching: Lecturer in CEM Kolaghat, 30/07/1999 to 05/09/2003
• Teaching: Lecturer, Ad-hoc in BPCIT, Krishnagar, 16/12/1997 to 29/07/1999

Research Paper published in International Journal

• Don’t care filling for power minimization in VLSI circuit testing by T. K. Maiti and S. Chattopadhyay, IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, USA, May 18-21, 2008, pp 2637-2640, 2008
• Input Assignment Technique for Low Power Circuit Testing by Subhadip Kundu, Kanchan Manna, T. K. Maiti and S. Chattopadhyay, 12th IEEE VLSI Design and Test Symposium (VDAT2008), Bangalore, India, July 23-26, pp 189-196, 2008
• Confidence Based Power Aware Testing by Subhadip Kundu, Kanchan Manna, T. K. Maiti and S. Chattopadhyay, 3rd International Symposium on Electronic system Design (ISED), BESU, Shibpur (Kolkata), WB, India, Dec 19-22, 2012

Research Paper published in International Conference

• Don’t care filling to Reduce Leakage Power in VLSI Circuit Testing by T. K. Maiti and S. Chattopadhyay, 8th IEEE Workshop on RTL and High Level Testing (WRTLT07), Beijing, China, Oct 12-13, 2007, pp 139-144, 2007

FDP/Seminar/Workshop/Conferences Organized

• Present IT Scenario Organized by  Dept. of CSE, RE College, Durgapur, during  18/12/1999 – 19/12/1999.

Summer/Winter Attended

• • State Level Seminar on “Present IT Scenario”, Dept. of CSE, RE College, Durgapur, from 18/12/1999 – 19/12/1999
  • Seminar on “Multimedia for IT Enabled Education”, held at SET, Dept. of Education Technology, JU, Kolkata in 2000.
  • Workshop on “Bioinformatics and its Application”, Dept. of Biotech, IIT, KGP, Sept. 26-27, 2003
  • National Seminar on “Applying Creativity and Systems Thinking for Business Innovation”, Hotel Taj Bengal, Kolkata, April 23-24, 2004, organized by Computer Engineering Division, WBSC, The Institute of Engineers (India).
  • Invited Speech on “Global Initiative on Workforce Development and vision of IBM IT Education Services”, Park Hotel, Kolkata, 30^th April, 2004.
  • In-house Workshop on “Design and Fabrication of Printed Circuit Board (PCB)”, Process Control Laboratory, Dept of ECE & EIE, CEM, Kolaghat, July 27-30, 2004.
  • Training Program on “Rational Rose Suit of IBM”, Multimedia Laboratory, Dept of CSE & IT, CEM, Kolaghat, November 6-7, 2004.
  • Orientation/Refresher Course on “VLSI Design & Testing”, Dept of CSE, Jadavpur University Campus, October 17-November 05, 2005.
  • Two-day Workshop on “Quality Enhancement of Engineering Education through NPTEL”, organized by Center for Education Technology, IIT, Kharagpur (at CET), March 27-28, 2006.